Test device and method for the SoC test architecture
US8555123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Feb 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test device for an SoC test architecture has a test input port, a test output port, a plurality of cores, a register, and a plurality of user defined logics. The register has a plurality of bits corresponding to the cores. Each of the user defined logics is connected to a corresponding bit of the register and a corresponding one of the cores. Each of the user defined logic receives a plurality of test control signals, and receives the corresponding bit of the register to change values of the test control signals. Outputs of each of the user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.