Apparatus and method for detecting an approaching error condition
US8555124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2010 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Feb 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus and includes a sequential storage structure arranged to latch an output signal generated by combinatorial circuitry dependent on a second clock signal. The sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry. The sequential storage structure can be operated in either first or second modes of operation where, in the first mode, the predetermined timing window is ahead of a time at which the main storage element latches said value of the output signal enabling an approaching setup timing error to be detected. In the second mode, the predetermined timing window is after the time at which the main storage element latches said value of the output signal where an approaching hold timing error is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.