Rate matching apparatus and rate matching method thereof
US8555133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Dec 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Provided is a rate matching apparatus. The rate matching apparatus includes interleavers, dummy bit removers, a bit collector, a memory and a selector. The interleavers interleave code blocks, respectively. The dummy bit removers remove dummy bits of the interleaved code blocks, respectively. The bit collector collects code blocks with the dummy bits removed by bit units, and divides a collected data bit stream into systematic data and parity data. The memory stores the systematic data and the parity data in parallel. The selector outputs in parallel a plurality of data bits which are selected from the systematic data and parity data of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.