Clock tree for pulsed latches
US8555227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.