Wire routing using virtual landing pads
US8555232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Feb 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for wire routing using virtual landing pads (VLPs) are described. In an embodiment, a method includes routing a wiring path between an output of a first circuit component and a VLP that represents an input of a second circuit component. For example, the VLP may have an area larger than the area of a physical pin of the second circuit component. The method may also include identifying a connection point on the VLP that is separated from an actual terminal of the second circuit, and completing the path between the connection point and the actual terminal. In some embodiments, the output of the first circuit component may also be represented by its own VLP. As such, systems and methods described herein may allow a circuit designer to perform routing procedures in a complex, highly integrated circuit, while reducing the circuit's overall capacitance and associated power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.