Patent · US Active

Method and apparatus for design rule violation reporting and visualization

US8555237B1 · kind B1 · utility

3Cited by

11References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Pardeep Juneja · Delhi, IN
Om Kanwar · Faridabad, IN
Harindranath Parameswaran · Noida, IN

Key dates

Filing date	Jul 5, 2012
Grant date	Oct 8, 2013
Priority date	—
Expiry date	Jul 5, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus and method for reporting design rule violations of an integrated circuit design includes collecting data from a design rule checker module, processing the data, and displaying design rule violations onto the layout. The display of the design rule violations may be interactive by including hypertext links to specifications, text bubbles with violation explanations, measurements, highlighting areas of the layout corresponding to a particular rule, and providing hierarchically expandable nodes for constraint violations in a browser.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.