Stacked semiconductor device and manufacturing method thereof
US8557635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Feb 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.