Semiconductor devices having nanochannels confined by nanometer-spaced electrodes
US8558326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Mar 27, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/958
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.