Patent · US Active

Fully digital method for generating sub clock division and clock waves

US8558589B2 · kind B2 · utility

5Cited by

7References

22Claims

0Family size

Assignee

DIALOG SEMICONDUCTOR INC. · DE

Inventors

Nir Dahan · Munich, DE
Kevin Allen · San Diego, US

Key dates

Filing date	Feb 22, 2012
Grant date	Oct 15, 2013
Priority date	—
Expiry date	Apr 5, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03K23/662
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The present disclosure provides circuitry and a method for digital clock generation including the generation of integer and non-integer sub clocks. The proposed method provides simplified constant signal propagation and low skew in the divided clock path independent of division factor. Also provided is a simplified mechanism for generating low power clock patterns divided down by factors which are non-integer, phase-shifted, repeated pulse trains, dynamically changing and glitch-free.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.