Phase noise tolerant sampling
US8558728B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Jul 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase noise in a first clock signal is measured using a time to digital converter (TDC) by determining variations in the phase delay between the first clock signal and a second clock signal. The TDC can include first and second series interconnections of delay elements, first and second sets of latches, and processing circuitry coupled to the latches and configured to determine the phase delay. The TDC can include a series interconnection of delay elements, latches, and circuitry configured to selectively adjust the control signal connected to the delay elements based on the output of the latches. The phase noise measurement can be used in a sampling circuit, so as to produce a second data signal from a first data signal based on the first clock signal and the measured phase noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.