Semiconductor memory device
US8559234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Feb 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a memory cell array, a first detecting circuit, a second detecting circuit, a switching circuit and a recovery control circuit. The first detecting circuit outputs a first detection signal which shows whether an externally supplied external power supply is equal to or more than a first voltage. The second detecting circuit outputs, at a higher speed than the first detecting circuit, a second detection signal which shows whether the external power supply is equal to or more than the first voltage. In a write operation, the switching circuit outputs the second detection signal output from the second detecting circuit. In an operation other than the write operation, the switching circuit outputs the first detection signal output from the first detecting circuit. The recovery control circuit terminates the write operation according to the second detection signal output from the switching circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.