Fractional-N dividers having divider modulation circuits therein with segmented accumulators
US8559587B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Mar 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.