System and method to reduce memory access latencies using selective replication across multiple memory ports
US8560757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Mar 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2532
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.