System and method for executing functional scanning in an integrated circuit environment
US8560903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2010 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Feb 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318544
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An example method is provided and includes executing a functional test for an integrated circuit and observing a failure associated with the integrated circuit. The method also includes executing a functional scan mode in order to reproduce the failure associated with the integrated circuit. A functional state of the integrated circuit is locked when the failure occurs, and the functional state is subsequently recovered for a structure test for the integrated circuit. In more particular embodiments, particular states of the functional test are evaluated and compared against other states associated with a model circuit that did not experience any failure in order to identify a latest cycle of the integrated circuit that could trigger the failure and an earliest cycle of the integrated circuit that could observe the failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.