Debugging external interface
US8560907B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2008 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Sep 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller has a first interface, for connection to an external memory device; a second interface, for connection to at least one other component; and a third JTAG interface, for connection to an external user device. The memory controller further includes a processor, which performs calibration processes, in order to synchronize operations of the memory controller and the external memory device, and also runs test software for testing operation of the first interface and the external memory device, and for providing test results to the external user device over the third interface. The memory controller further includes an internal memory, for storing the instructions defining the test software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.