Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design
US8561005B2 · kind B2 · utility
3Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Apr 22, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Apr 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.