Synchronization coverage in logic code
US8561031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Sep 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for enhancing synchronization coverage for a logic code is provided. The method comprises tracking whether one or more code sections in the logic code are blocked by at least another code section in the logic code, or whether one or more code sections in the logic code are blocking at least another code section in the logic code, during one or more test runs; and including one or more delay mechanisms in the logic code to introduce a delay in execution of a first code section in the logic code, wherein length of introduced delay is dependent on whether the first code section was blocked by a second code section or whether the first code section was blocking the second code section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.