Methods for manufacture a capacitor with three-dimensional high surface area electrodes
US8561271B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Dec 15, 2010 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Aug 17, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/435
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for making a capacitor having improved capacitance efficiency which results from increasing the effective area of an electrode surface is disclosed. Specifically, an improved “three-dimensional” capacitor may be constructed with electrode layers having three-dimensional aspects at the point of interface with a dielectric such that portions of the electrode extend into the dielectric layer. Advantageously, embodiments of a three-dimensional capacitor drastically reduce the space footprint that is required in a circuit to accommodate the capacitor, when compared to current capacitor designs. Increased capacitance density may be realized without using high k (high constant) dielectric materials, additional “electrode-dielectric-electrode” arrangements in an ever increasing stack, or serially stringing together multiple capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.