Methods, apparatus and computer program products for fabricating masks and semiconductor devices using model-based optical proximity effect correction and lithography-friendly layout
US8563197B2 · kind B2 · utility
2Cited by
0References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2008 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Apr 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.