Thin film transistor array substrate and manufacturing method for the same
US8563341B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2012 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Feb 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
Abstract
The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.