Semiconductor storage device and method for manufacturing same
US8563961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2010 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Dec 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.