Circuit architecture for metal oxide semiconductor (MOS) output driver electrical overstress self-protection

US8564065B2 · kind B2 · utility

Assignee

• Analog Devices, Inc. · US

Inventors

• Colm Donovan · Leap, IE
• Javier Alejandro Salcedo · North Billerica, US

Key dates

• Filing date: Jun 3, 2011
• Grant date: Oct 22, 2013
• Expiry date: Feb 13, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/819

Abstract

Metal oxide semiconductor (MOS) protection circuits and methods of forming the same are disclosed. In one embodiment, an integrated circuit includes a pad, a p-type MOS (PMOS) transistor, and first and second n-type MOS (NMOS) transistors. The first NMOS transistor includes a drain, a source and a gate electrically connected to the pad, a first supply voltage, and a drain of the PMOS transistor, respectively. The second NMOS transistor includes a gate, a drain, and a source electrically connected to a bias node, a second supply voltage, and a source of the PMOS transistor, respectively. The source of the second NMOS transistor is further electrically connected to a body of the PMOS transistor so as to prevent a current flowing from the drain of the PMOS transistor to the second supply voltage through the body of PMOS transistor when a transient signal event is received on the pad.