Semiconductor device and manufacturing method therefor
US8564093B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2009 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jan 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a semiconductor device and a manufacturing method for the same, and makes the rejection rate of the product after chips are stacked and mounted sufficiently low, even when the chips are selected in a conventional, simple and inexpensive wafer test.A first device where a number of first semiconductor chips and a second semiconductor chip for controlling communication between the first semiconductor chips and the outside or communication between the first semiconductor chips are stacked and a second device having at least one third semiconductor chip that communicates with the second semiconductor chip are mounted on a substrate, wherein the third semiconductor chip functions to substitute a first semiconductor chip, there are at least the same number of third semiconductor chips as there are first semiconductor chips that do not operate normally, from among the first semiconductor chips within the first device, and the third semiconductor chips are stacked so as to substitute the functions of the first semiconductor chips that do not operate normally.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.