Stacked digital/RF system-on-chip with integral isolation layer
US8564111B2 · kind B2 · utility
0Cited by
0References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 27, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jan 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a device package, a first Integrated Circuit (IC) that is packaged in the device package, and a second IC, which is packaged in the device package and is fabricated on a multi-layer interconnection circuit including a plurality of interconnection layers for interconnecting components of the second IC, wherein a selected layer in the plurality is configured to serve as a conductive shield for reducing interference between the first and second ICs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.