Dual phase-locked loop circuit and method for controlling the same

US8564340B2 · kind B2 · utility

Assignee

• MSTAR SEMICONDUCTOR, INC. · TW

Inventors

• Yong Liu · Rye, US
• Wen cai Lu · Shanghai, CN
• Sterling Smith · Hsinchu, TW

Key dates

• Filing date: Jun 29, 2010
• Grant date: Oct 22, 2013
• Expiry date: Nov 30, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/0995
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.