Method and system for controlling HS-NMOS power switches with slew-rate limitation
US8564359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2010 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Oct 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.