Device and method for reducing impedance
US8564967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2007 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Mar 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.