Low latency frequency switching
US8565121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2007 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jul 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/3036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer. In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control and gain control are iterated to perform gain calibration, with signaling to control the iterations without need for processor intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.