MAC address table collection in distributed switching systems
US8565251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Dec 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3009
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In accordance with embodiments of the present disclosure, a switch may include a processor and a plurality of line cards, each line card including a table of addresses. The processor may be configured to: (i) read, from a first line card of the plurality of line cards, addresses relating to all flooding domains present on the first line card; (ii) store the addresses read from the first line card on a memory accessible to the processor; (iii) determine a second line card of the plurality of line cards, the second line card having the presence of at least one flooding domain not present on the first line card; (iv) read, from the second line card, addresses relating to all flooding domains present on the second line card; and (v) store the addresses read from the second line card on the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.