Scanning signal line drive circuit and display device having the same
US8565369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2010 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Oct 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bistable circuit includes an input terminal (41) for a set signal, an input terminal (42) for a reset signal, an output terminal (48) for a state signal, a thin-film transistor (M2) for increasing a potential of the output terminal (48) based on a first clock, a thin-film transistor (M1) for increasing a potential of a first-node connected to a gate terminal of the thin-film transistor (M2) based on the set signal, a thin-film transistor (M5) for decreasing the potential of the first-node, a thin-film transistor (M7) for increasing a potential of a second-node connected to a gate terminal of the thin-film transistor (M5) based on the reset signal, a thin-film transistor (M6) for decreasing the potential of the output terminal (48) based on the potential of the second-node, a thin-film transistor (M3) for increasing the potential of the second-node based on the set signal, and a capacitor (CAP2) having one end connected to the second-node and the other end connected to the input terminal (41).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.