Combined spike domain and pulse domain signal processing
US8566265B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Feb 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neural network has an array of interconnected processors, at least a first processor in the array operating in a pulse domain and at least a second processor in the array operating in a spike domain, and each said processor having: first inputs selectively coupled to other processors in the array of interconnected processors, each first input having an associated VCCS (a 1 bit DAC) coupled to a summing node, second inputs selectively coupled to inputs of the neural network, the second inputs having current generators associated therewith coupled to said summing node, a filter/integrator for generating an analog signal corresponding to current arriving at the summing node, and for processors operating in the pulse domain, an analog-to-pulse converter for converting an analog signal derived either directly from the filter/integrator or via a non-linear element, to the pulse domain, and providing the converted analog signal as an unquantized pulse domain signal at an output of each processor operating in the pulse domain and for processors operating in the spike domain, an analog-to-spike converter for converting an analog signal derived either directly from the filter/integrator or…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.