Intelligent write caching for sequential tracks
US8566518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2012 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | May 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0868
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.