Systems and methods for destaging storage tracks from cache
US8566535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2012 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jun 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.