Edge memory architecture for LDPC decoder
US8566668B1 · kind B1 · utility
8Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jun 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1137
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, devices, and methods are disclosed for a novel edge memory architecture. An architecture is described wherein the extrinsic information typically stored inside the edge memory is reformatted. Instead of storing the extrinsic information for every edge, the novel edge memory stores a set of possible extrinsic information values for a check node in a “value memory.” The edge memory also stores an index for each edge in a second, “index memory,” identifying which value stored in the value memory applies to each respective edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.