Three-dimensional integrated circuit design device, three-dimensional integrated circuit design, method, and program
US8566762B2 · kind B2 · utility
197Cited by
0References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2012 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Feb 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A worst-case temperature calculation unit calculates, based on heat value information of each layer of a three-dimensional integrated circuit to be designed and stack structure information of the three-dimensional integrated circuit, a worst-case temperature of a layer during operation that is targeted for logic synthesis. A logic synthesis library selection unit selects a library appropriate for the calculated worst-case temperature. A logic synthesis unit performs logic synthesis on the targeted layer with use of the selected library.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.