In-hierarchy circuit analysis and modification
US8566765B1 · kind B1 · utility
8Cited by
4References
51Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2010 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Nov 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Modifying a hierarchical circuit design includes accessing hierarchical circuit data in the hierarchical circuit design; performing timing analysis and modifications on a selected portion of the hierarchical circuit data to achieve inter-block timing closure; and performing timing analysis and modifications on the hierarchical circuit data, while accounting for a modification made on the selected portion of the hierarchical circuit data, to achieve intra-block timing closure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.