Cooperative multi-level scheduler for virtual engines
US8566829B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2008 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | May 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/524
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for providing a plurality of virtual machines utilizes a multi-core processor having a plurality of cores, each with a memory cache, and a shared memory resource in communication with the cores. The device utilizes a cooperative, multi-level scheduler. The multi-level scheduler includes a primary scheduler and a plurality of secondary schedulers, each supporting a subset of the physical cores. The primary scheduler assigns a group of threads to one of the processor cores. The secondary scheduler associated with the processor core to which the group of threads was assigned schedules execution of individual ones of the threads. The secondary scheduler also provides an indication of lock status to the primary scheduler. The lock status information can be used by the primary scheduler to avoid preempting a thread that holds a lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.