Electronic arrangements for passivated silicon nanowires

US8569741B2 · kind B2 · utility

Assignee

• CALIFORNIA INSTITUTE OF TECHNOLOGY · US

Inventors

• Axel Scherer · Laguna Beach, US
• Sameer Walavalkar · West Hollywood, US
• Michael David Henry · Tucson, US
• Andrew Homyk · South Pasadena, US

Key dates

• Filing date: Oct 31, 2011
• Grant date: Oct 29, 2013
• Expiry date: Mar 6, 2032

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/762
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches.