Storage device comprising semiconductor elements
US8569753B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Nov 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.