MOS devices with improved source/drain regions with SiGe
US8569846B2 · kind B2 · utility
1Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Jun 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.