Nano thick Pt metallization layer
US8569889B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Nov 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S2301/176
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A metallization layer for a semiconductor device includes a first layer made of Pt and having a thickness greater than or equal to 15 Å and less than or equal to 50 Å, and a second layer formed on the first layer and made of a plurality of metallic sub-layers such as Ti/Pt/Au. A semiconductor device fabricated from the metallization layer includes a semiconductor substrate having a top layer and mesa structure and corresponding surface for securing an insulating layer and a corresponding exposed surface, and wherein the metallization layer is deposited over the insulating layer and exposed surface. Methods for forming the metallization layer are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.