Circuit for reducing negative bias temperature instability
US8570068B2 · kind B2 · utility
3Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Sep 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.