Clock gating cell circuit
US8570069B2 · kind B2 · utility
7Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2012 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Apr 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.