Phase adjustment apparatus and clock generator thereof and method for phase adjustment
US8570071B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 4, 2012 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Jan 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.