Image processing circuit and method thereof
US8570443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Jan 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, a plurality of line buffers, a first sharpness circuit, a second scaling circuit, and a second sharpness circuit. The first scaling circuit enlarges an input image along a first direction to generate a first enlarged image. The line buffers temporarily store the pixel values of a plurality of pixel rows of the first enlarged image. The first sharpness circuit vertically sharpens the first enlarged image to generate a first sharpened image. The second scaling circuit enlarges the first sharpened image along a second direction to generate a second enlarged image. The second sharpness circuit horizontally sharpens the second enlarged image to generate a second sharpened image. Accordingly, it is possible to use the line buffers having shorter data lengths to perform the vertical sharpening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.