Memory devices and methods for high random transaction rate
US8570790B2 · kind B2 · utility
3Cited by
10References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Feb 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines independently and concurrently in synchronism with at least a first clock signal; an address port configured to receive address values on consecutive, different transitions of a second clock, each address value corresponding to an access on a different one of the data ports; and a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.