Nonvolatile memory device with 3D memory cell array
US8570808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Nov 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.