Receiver
US8571504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2012 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Mar 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45511
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A receiver (400; 500) comprising an amplifier (406; 506) having an input (408) and an output (410). The input (408) of the amplifier is configured to receive a signal. The receiver also comprises a feedback path (412; 512) between the output (410) and the input (408) of the amplifier (406; 506), wherein the feedback path (412; 512) includes a filter (402; 502) and a buffer amplifier (414; 514) in series. The input of the buffer amplifier (414; 514) is connected to the output (410; 510) of the amplifier (406; 506). The output of the buffer amplifier (414; 514) is connected to the input of the filter (402; 502). The output of the filter (402; 502) is connected to the input (408; 508) of the amplifier (406; 506). The filter (402; 502) is configured to pass signals having a desired frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.