Low-power biasing networks for superconducting integrated circuits
US8571614B1 · kind B1 · utility
60Cited by
4References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | May 19, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49124
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.