Hardware accelerator module and method for setting up same

US8572299B2 · kind B2 · utility

Assignee

• Intel Mobile Communications Technology Dresden GmbH · DE

Inventors

• Uwe Pross · Chemnitz, DE
• Tobias Weber · Verl, DE
• Gunnar Nitsche · Hildesheim, DE
• Thomas Fliess · Dresden, DE

Key dates

• Filing date: Oct 3, 2011
• Grant date: Oct 29, 2013
• Expiry date: Oct 3, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3881
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.